This application claims the priority of Korean Patent Application No. 2002-57462 filed on Sep. 19, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an electrode line structure having a fine line width and a method of forming the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, fine circuit patterns having a fine line width or electrode lines having a fine line width are required. In particular, electrode lines such as word lines or bit lines are of the most widely used lines in a DRAM (dynamic random access memory) device, and the line width of the electrode lines is considered to be the barometer of the level of integration and performance of the highly-integrated semiconductor device.
Generally, electrode lines are formed by patterning a conductive layer via a photolithography process using an exposure-based optical system capable of achieving high-resolution.
However, as the integration density of the semiconductor devices increases exponentially, it is desirous for the word lines and the bit lines to have a line width not larger than the exposure limit, which results in the following problems.
With reference to FIGS. 1A to 1C, as shown in FIG. 1A, a conductive layer 12 and a hard mask layer 14 are deposited on an upper portion of a semiconductor substrate 10 in order to form electrode lines, for example, word lines. Thereafter, photoresist patterns 16 for defining the word lines are formed by a known photolithography process. The expected line width of the word lines is not larger than the exposure limit, and is currently about 0.1 μm. However, if the photoresist patterns 16 having a line width not larger than the exposure limit are disposed at fine intervals, edges of upper portions of the photoresist patterns 16 become rounded due to the proximity effect and due to the photo-interference generated when exposing the photoresist patterns 16. As a result, side walls of the photoresist patterns 16 tend to become inclined.
The hard mask layer 14 and the conductive layer 12, which are formed under the photoresist patterns 16, are patterned using the above photoresist patterns 16 to form word lines 20. Since the word lines 20 thus formed have the same profile as the photoresist patterns 16, edges of upper portions of the word lines 20 are rounded, and side walls of the word lines 20 are inclined.
The side walls of the word lines 20 are inclined not only in the channel length direction (short axis direction of the word lines 20), as shown in FIG. 1B, but also in the channel width direction (long axis direction of the word lines 20), as shown in FIG. 1C. After removing the photoresist patterns 16 using a known method, an insulating layer for a spacer (not shown) is deposited on an upper portion of the resultant structure in order for a subsequent self-aligned contact step to be performed. Then, the insulating layer to be formed into a spacer is etched by an anisotropic blanket etching method to form a spacer 22. Since the side walls of the word lines 20 become inclined during the etching step for forming the spacer 22, the insulating layer formed on the inclined side walls of the word lines 20 is exposed to a large amount of anisotropic etching gas. Therefore, as shown in FIG. 1C, only a small amount of the spacer 22 remains on a portion of the side walls of the word lines 20. The spacer 22 may be even partially removed at a portion of the inclined side walls of the word lines 20, thereby exposing a portion of the word lines 20. Particularly, in the case where the word lines 20 are made of a material that is susceptible to the wet etching chemical, such as SC1 (standard chemical 1), for example, a material containing tungsten, large portions of the word lines 20 are removed during the subsequent wet etching step. A line defect is therefore generated in the semiconductor device due to the removal of a large portion of the word lines 20.
FIG. 2 is a SEM (scanning electron microscope) photograph of a conventional gate line, and FIG. 3 is a photograph of a plan view of a conventional semiconductor device.
In a case where the word lines 20 are formed using the photoresist patterns 16 having the fine line width and the fine space, it can be seen from FIG. 2 that the side walls of the word lines 20 are inclined. In FIG. 2, reference character A represents the inclined surface of the side walls.
When a subsequent etching step is preformed in the case where a portion of the spacer 22 has been removed, it can be seen from FIG. 3 that a portion of the word lines 20 are also removed. In FIG. 3, reference character B represents defects of a line shape indicating the removed portion of the word lines 20.